1. Field of the Invention.
This invention relates to a method and apparatus for achieving ultra high density integrated circuit packages incorporating a plurality of ultra-thin encapsulated integrated circuit packages stacked and interconnected into an ultra-high density three-dimensional module.
More specifically, this invention relates to apparatus and methods of fabricating ultra high density integrated circuit packages using high temperature flexible material to bind individual integrated circuit packages together in a stack configuration forming composite ultra high density integrated circuit packages.
2. Discussion of the Related Art
Packaging techniques for integrated circuits (ICs) have been developed in the past in an attempt to satisfy demands for miniaturization in the semiconductor industry. Improved methods for miniaturization of integrated circuits enabling the integration of millions of circuit elements into single integrated silicon embodied circuits, or chips, have resulted in increased emphasis on methods to package these circuits in space efficient, yet reliable and mass producible packages. Various methods and apparatus for fabricating ultra high density integrated circuits have been developed. Reference is hereby made to related and co-pending applications Ser. No. 07/884,066, filed May 15, 1992 and Ser. No. 07/561,417, filed Aug. 1, 1990, which are incorporated into the present application by reference.
Application Ser. No. 07/884,066 describes the construction of a modular level-two package comprised of a plurality of stacked level-one packages, which are laminated together using adhesive between each level-one package and a foil adhesive layer adhered to the top of the upper most level-one package and the bottom of the lower most level-one package in the level-two stack, or package. That application also discloses a method of forming a level-two stack of level-one packages whereby the level-two stack is connected to a rail assembly, which contains a shoulder and an extension with tabs. Tabs on the rail extension are secured to a cap at the top of the level-two stack to hold the stack in alignment. The rail shoulder prevents the rail extension tabs from causing an electrical short in the package. The rail provides electrical connections to the package and also provides improved heat dissipation from the package since the rail is connected to leads from the individual level-one packages in the level-two stack which extend outwardly from the individual level-one packages and are soldered onto the rail.
Application Ser. No. 07/561,417 describes a packaging technique whereby a level-two package is fabricated from level-one integrated circuits which are bound together using an epoxy adhesive applied between each level-one package and contain a metal foil which is applied to the top most and bottom most level-one package in the level-two package. That application also describes a method of mechanically binding the level-one packages together by using means such as a tie or a housing.
The introduction of highly sophisticated integrated circuit microprocessors led to the rapid development of complex personal computers and other common bus systems utilizing a variety of integrated circuit elements such as memory devices (DRAMS, VRAMS, FLASH ROMs, E PROMS, and SRAMS), programmable logic arrays (PLAs), microprocessors (CPUs), co-processors, and other related integrated circuit elements which had to be assembled, mounted and interconnected into as compact, yet reliable packages as feasible to satisfy the industry demands for miniaturization.
Other key considerations in developing packaging for such circuits have been the cost of manufacture, the reliability of the packaged device, heat transfer, moisture penetration, standardization of mounting and interconnect methods, and the ability to test and control the quality of the packaged devices.
In the past, one area of concentration for high density packaging has been memory devices such as SRAMS and DRAMS. Prior systems typically utilized a transfer molded plastic encasement surrounding the integrated circuit and having one of a variety of pin-out or mounting and interconnect schemes. The older M-DIP (Dual-In-line-Plastic) provides a relatively fiat, molded package having dual parallel rows of leads extending from the bottom for through-hole connection and mounting to an underlying circuit board substrate. These packages provided 100 mil spacing between leads.
A more dense package was the 100 mil SIP (Single-In-Line-Plastic) which was assembled on edge with two rows of 100-mil staggered leads extending from the bottom edge for through-hole assembly.. Another popular prior art package is the PLCC (Plastic Leaded Chip Carrier) SOJ (Small Outline J-leaded) molded package with twenty surface-mount designed J-leads (length 0.67", width 0.34", height 0.14"). This prior art package is illustrated schematically in FIG. 1 and shown at approximate actual size in FIG. 2.
In order to obtain more density and provide lower cost socketability (i.e. removable mounting) and to allow for after-market sale of additional memory units, the SIMM (Single-In-Line Memory Module) was developed. This package is schematically illustrated in FIG. 3. In this package typically nine one-megabyte or four-megabyte DRAMS were surface mounted into a socket which was in turn edge-mounted on a large circuit board substrate containing additional sockets or components. While this design provided some increase in density, it had the drawback of providing a module extending from one-half to nearly two inches vertically above the circuit board substrate.
Newer, higher density versions of the SIMM design with even smaller versions of the DRAM plastic package have been developed. These thinner versions of SOJ DRAMS are one-half the thickness (having a plastic packaging thickness of about 70 mils) of standard SOJ designs, and have been mounted on both sides of circuit board substrates. Even smaller TSOP packages have been developed experimentally with a plastic thickness of one millimeter and lower profile gull-wing leads for surface mounting. FIGS. 1-3 illustrate typical embodiments of some of these prior art packages. Based on experience with those prior art designs, for reasons of reliability related to moisture penetration and mechanical integrity, the industry has adopted a standard thickness for plastic packaging of approximately one millimeter (40 mils), or approximately 10.5 mils on each side of a 11 mil thick integrated circuit element attached to a 8 mil thick lead frame.
In contrast to such prior art systems, the packaging method of the present invention provides a reliable, cost efficient, easily manufacturable package with a plurality of ultra thin level-one package elements assembled in an integrated module or level-two package which can be mounted to a circuit board substrate directly or via an underlying socket or header.
Key considerations in developing packaging for such high density circuits have been the cost and simplicity of manufacture, reliability, heat transfer properties, moisture penetration, standardization of mounting and interconnect methods, and the ability to test and control the quality of the packaged devices.